1. Field of the Invention
This invention relates to processors and, more particularly, to scheduling and coordination of instruction execution within a processor.
2. Description of the Related Art
In some pipelined processor embodiments implementing a given instruction set architecture (ISA), different instructions may be configured to execute with different latencies according to their relative complexity. For example, multiplication instructions may execute in a greater number of execution cycles than add instructions. In some such embodiments, two instructions that begin execution in two different execution cycles may complete execution and produce a result to be written back (for example, to a register file) during the same execution cycle.
Providing a dedicated write port for each instruction of differing latency may be expensive in terms of design effort, manufacturing cost, and processor performance, as additional write ports typically require increased processor die area, which may in turn reduce usable die per wafer and lengthen critical circuits. Further, if a write conflict between differing-latency instructions is relatively rare, dedicated write ports may be poorly utilized.
On the other hand, requiring differing-latency instructions to arbitrate for a write port may also increase design complexity and impact performance. For example, if a given instruction loses arbitration and cannot write back during a given execution cycle, its result may need to be queued for another arbitration attempt, or execution may stall until writeback can proceed. Additionally, if an arbitration algorithm is not designed and verified to be fair, performance of certain types of instructions could suffer. In the worst case, a livelock or deadlock condition could arise if a given instruction is queued or stalled indefinitely while waiting for writeback.